The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB. The core is compatible with the Philips I²C standard and supports 7- and 10-bit addressing with an optionally software programmable address. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.
- AMBA APB interface
- Optional programmable I²C address - The initial address is configurable via a VHDL generic. The designer can choose to leave the core's address programmable via an APB mapped register.
- 10-bit address support. If the core is configured without a hard coded address software may also configure the core to use 7-bit addressing.
- Four main modes, core can be configured to force a master into wait mode by lowering the SCL line during reception and/or transmission. See GRIP manual for details.
- Clock stretching
For more information, please see the GRLIB IP Core User's Manual
- The I²CSLV core uses approximately 150 LUTs on Xilinx Virtex 2 technology.
- The core is available under a commercial license and also under the GPL.