The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple ethernet packets can be received and transmitted without CPU involvement. The GRETH supports the MII and RMII PHY interfaces. Hardware support is also provided for the EDCL UDP debugging protocol. For critical space applications, a fault-tolerant version of GRETH is available with full SEU protection of all RAM blocks.
The EDCL is an optional hardware unit providing read/write access to the AHB bus through ethernet using an UDP based protocol. It operates in parallel with the MAC DMA and does not interfere with the normal network traffic other than lowering performance. Speeds up to 90 Mbit/s effective throughput have been achieved when accessing the AHB bus through the EDCL using the GRMON debug monitor.
The GRETH is inherently portable and can be implemented on most FPGA and ASIC technologies. The table below shows the approximate area and frequency for two different GRETH configurations on Altera Stratix, Xilinx Virtex2 and ASIC technologies.
(LUTs / RAM / Frequency) Virtex
(ALMs / M4K / Frequency) Stratix
|Configuration||Stratix II||Virtex2||ASIC gates
|GRETH||731 / 4 / 130||1,600 / 2 / 90||10,000|
|GRETH + EDCL||1,129 / 6 / 130||2,500 / 4 / 90||13,000|
The GRETH core is freely available in VHDL source code under the GNU GPL license. It can also be licensed commercially, either stand-alone or as part of the GRLIB IP library.