Cobham Gaisler AB provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. We specialize in digital hardware design for both commercial and aerospace applications



Mezzanine board for GR-CPCI-AX2000 board, providing:

  • 128k x 40 bit EEPROM memory (32 bit data, 8 bit checksum)(Hitachi HN58C1001T)
  • 10/100 Ethernet PHY, primary interface
  • 10/100 Ethernet PHY, secondary interface
  • Redundant channel MIL-STD-1553 interface, primary bus
  • Redundant channel MIL-STD-1553 interface, secondary bus
  • Redundant CAN interface based on RS-485 transceivers (TI SN65HVD12)
  • Headers for General Purpose I/O connections
  • Socket for oscillator
  • Reset button

Note: One Ethernet interface shares signals with one MIL-STD-1553 interface, allowing only one of them being used at a time.

This board is compatible with the following products:

  • GR-CPCI-AX2000
  • GR-MCC-C (only supporting one 10/100 Ethernet interface, and no EEPROM)

An alternative Mezzanine board design with similar MIL-STD-1553, CAN and Spacewire features is available for the GR-CPCI-XC2V Development Board: GR-CPCI-1553


Document File
Schematic & Assembly Drawing GR-RTAX-MEZZ-2_assy_dwg