Quad-Core LEON4 Evaluation Board
Note: The GR-CPCI-LEON4-N2X board is out of stock and no further production is planned. Please see the GR-CPCI-GR740 development board instead.
The GR-CPCI-LEON4-N2X evaluation board has been designed for evaluation of the Cobham Gaisler LEON4 Next Generation Microprocessor (NGMP) functional prototype device. The prototype is a system-on-chip with four 32-bit LEON4 SPARC V8 processor cores connected to a shared 256 KiB Level-2 cache and several high-speed interfaces, including an 8-port SpaceWire router and dual gigabit Ethernet interfaces. The architecture provides improved support for debugging and software partitioning together with extended support for both symmetric and asymmetric multiprocessing. The space-grade successor for this NGMP functional prototype is the Rad-Hard GR740 device. There are several differences between the GR740 device and the LEON4-N2X functional prototype and users who intend to target GR740 are recommended to use the GR-CPCI-GR740 development board.
The board is a custom designed PCB in a 6U Compact PCI (CPCI) format, making the board suitable for stand-alone bench top development, or if required, to be mounted in a 6U CPCI Rack. The principle interfaces and functions are accessible on the front and back edges of the board, and secondary interfaces via headers on the board.
- DDR2 SDRAM SODIMM sockets, providing 96-bit wide interface with up to 2 GiB of data memory
- PC100 SDRAM, 96-bit wide interface providing 128 MiB of data memory
- NOR Flash PROM, 8 MiB, both 8- and 16-bit wide operation
- Dual 10/100/1000 Mbit Ethernet interface
- Dual-redundant MIL-STD-1553B interface
- 8-port SpaceWire interface
- SpaceWire Debug Communication Link interface
- 16 bit General Purpose I/O (ribbon cable style connector)
- USB-to-Serial interface providing access to UARTs and JTAG debug interface
- Compact PCI interface (32 bit, 33/66MHz), configurable for Host or Peripheral slot
- Input power connectors for stand-alone use
- DIP switches for GPIO and bootstrap signal configuration
- LED indicators
- SPI interface
- Two Serial UART interface (RS232)
- JTAG debug interface
- DDR2-600 SDRAM, 1 bank 96 bits wide, DDR2-SODIMM sockets
- PC100 SDRAM, 1 bank 96 bits wide, 6x256 Mbit, discrete chips
- Parallel Boot Flash (64 Mbit, both 8- and 16-bit wide operation)
There are differences in between the GR740 device and the NGMP functional prototype and these are described in the GR740 Comparison document available on the GR740 product page.
|GR-CPCI-LEON4-N2X Quick Start Guide||GR-CPCI-LEON4-N2X-QSG.pdf (updated 2013-July)|
|GR-CPCI-LEON4-N2X Board Package||gr-cpci-leon4-n2x-bp-v04.zip (updated 2013-July)|
|GR-CPCI-LEON4-N2X Board User Manual||GR-CPCI-LEON4-N2X_UM.pdf (updated 2018-March)|
|LEON4-N2X Data Sheet and User's Manual||LEON4-N2X-DS.pdf (updated 2015-April)|
|Technical Note on LEON SRMMU Behaviour||GRLIB-TN-0002.pdf|
|Handling denormalized numbers with the GRFPU||GRLIB-AN-0007.pdf|