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Bai Hong Fang, Qiang Xu and Nicola Nicolici Department of Electrical and Computer Engineering McMaster University, Hamilton, ON L8S 4K1, Canada

A novel approach for testing embedded memories in com-plex systems-on-a-chip (SOCs) is presented. The proposed solution aims to balance the usage of the existing on-chip resources and dedicated design for test (DFT) hard-ware such that the functional power constraints are not ex-ceeded during test while trading-off the testing time against DFT area and performance overhead. The suitability of software-centric and hardware-centric approaches for em-bedded memory testing is examined and to combine the ad-vantages of both directions, a new built-in self-test (BIST)-based method, called hardware/software co-testing, is in-troduced. The proposed solution is programmable, scalable and guarantees low routing overhead.